Show HN: Fursoy – Out-of-order RV64IMAFDV core in SystemVerilog (Linux 6.6)
Submitted by fursoy. Show HN recorded 59 points and 19 comments as of Nov 14, 2026 (UTC).
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Recorded metrics
points · 59 votes
2026-11-14 21:57:49.542Z
cumulative since publication
Research analysis
Project record
Repository: FURSOY/fursoy-cpu. The record contains the title “Show HN: Fursoy – Out-of-order RV64IMAFDV core in SystemVerilog (Linux 6.6)” but no substantive source summary.
Observed adoption & comparisons
Source votes: 59 votes (Nov 14, 2026 UTC; cumulative since publication)
Adoption decision
Evaluate it against the tool or manual workflow it would replace. The stored record supports discovery; it does not yet establish reliability, lower operating cost or commercial adoption.
Unverified requirements
Not verified: license permissions, required hardware, installation steps, maintenance status and a representative task with its failure cases.
Next test
Choose one real task and a current alternative. Record the commit, environment, input, output, elapsed time and failure behavior; retain the result before recommending adoption.